1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device arranged at a crossing portion of a word line and first and second bit lines.
2. Description of the Background Art
FIG. 24 is a circuit diagram showing the configuration of a memory cell 90 in a conventional static random access memory (hereinafter referred to as SRAM). In FIG. 24, memory cell 90 includes P-channel MOS transistors 91, 92 and N-channel MOS transistors 93 to 96. P-channel MOS transistors 91, 92 are connected between the lines of a power- supply potential VDD and storage nodes N91, N92 respectively, and have gates connected to storage nodes N92, N91 respectively. N-channel MOS transistors 93, 94 are connected between storage nodes N91, N92 and the lines of a ground potential GND respectively, and have gates connected to storage nodes N92, N91 respectively. N-channel MOS transistors 95, 96 are connected between storage nodes N91, N92 and bit lines BL, /BL respectively, and have gates both connected to a word line WL. MOS transistors 91, 93 form an inverter that applies an inversion signal of a signal at storage node N92 to storage node N91. MOS transistors 92, 94 form an inverter that applies an inversion signal of a signal at storage node N91 to storage node N92. The two inverters are connected between storage nodes N91 and N92 in back-to-back connection, forming a latch circuit.
At writing operation, word line WL is set to a logic high or an xe2x80x9cHxe2x80x9d level of a selective level to render N-channel MOS transistors 95, 96 conductive. If one of bit lines BL, /BL (BL for example) is set to the H level while the other bit line (/BL in this example) is set to a logic low or an xe2x80x9cLxe2x80x9d level in response to a write data signal, MOS transistors 91, 94 are rendered conductive while MOS transistors 92, 93 are rendered non-conductive, latching the level of storage nodes N91, N92. If word line WL is set to the L level of a non-selective level, N-channel MOS transistors 95, 96 are rendered non-conductive, and a data signal is stored into memory cell 90.
At reading operation, bit lines BL, /BL are pre-charged to the H level, and thereafter word line WL is set to the H level of the selective level. This allows current to flow out an the lines of ground potential GND from a bit line (/BL in this example) through N-channel MOS transistors 96 and 94, lowering the potential of bit line /BL. By comparing the potential of bit line BL with the potential of bit line /BL, stored data in memory cell 90 can be read out.
FIG. 25 is a circuit diagram showing the configuration of a memory cell 100 in a conventional content addressable memory (hereinafter referred to as CAM). Referring to FIG. 25, memory cell 100 is configured by adding N-channel MOS transistors 101 to 103 to memory cell 90 in FIG. 24. In CAM, a match line ML is provided per word, and a plurality of memory cells 100 corresponding to one word are connected to one match line ML. N15 channel MOS transistors 101, 102 are connected between bit lines BL, /BL and node N101 respectively, and have gates connected to storage nodes N91, N92 respectively. N-channel MOS transistor 103 is connected between match line ML and the line of ground potential GND, and has the gate; connected to node N101 arranged between N-channel MOS transistors 101 and 102.
Data writing/reading are performed using word line WL and bit line pair BL, /BL, as in the SRAM in FIG. 24. At data retrieval, match line ML is pre-charged to the H level, and thereafter an inversion data signal of a data signal to be retrieved is applied to bit lines BL, /BL. If storage data are xe2x80x9c0xe2x80x9d and xe2x80x9c1,xe2x80x9d storage nodes (N91, N92) have (0, 1) and (1, 0) respectively. *If the data to be retrieved are xe2x80x9c0xe2x80x9d and xe2x80x9c1,xe2x80x9d bit lines (BL, /BL) are provided with (1, 0) and (0, 1).
If, for example, the storage data is xe2x80x9c0xe2x80x9d and the retrieval data is xe2x80x9c0,xe2x80x9d storage nodes (N91, N92) have (0, 1), rendering N-channel MOS transistor 101 non-conductive and N-channel MOS transistor 102 conductive. Here, bit lines (BL, /BL) have (1, 0), so that node N101 is set to the L level. Thus, N-channel MOS transistor 103 is rendered non-conductive, while match line ML remains at the H level. If the stored data is xe2x80x9c1xe2x80x9d whereas the retrieval data is xe2x80x9c0,xe2x80x9d storage nodes (N91, N92) have (1, 0), rendering N-channel MOS transistor 101 conductive and N-channel MOS transistor 102 non-conductive. Here, bit lines (BL, /BL) have (1, 0), 50 that node N101 is set to the H level. Thus, N-channel MOS transistor 103 is rendered conductive, lowering match line ML to the L level.
That is, if there is even one bit of a plurality of data pieces included in one word that does not match with a retrieval word, match lines ML corresponding to that word are lowered to the L level (xe2x80x9c0xe2x80x9d). Only match line ML corresponding to a word having all bits matching with the retrieval word is held at the H level (xe2x80x9c1xe2x80x9d).
Thus, each of the conventional memory cells 90 and 100 had only two types of data holding states. Accordingly, if the data signal had three values of xe2x80x9c0,xe2x80x9d xe2x80x9c1xe2x80x9d and xe2x80x9cx,xe2x80x9d two memory cells, i.e. a memory cell holding xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d and a memory cell holding xe2x80x9cxxe2x80x9d which indicates whether data is valid or invalid, had to be used as one set. This increased the area occupied by the memory, resulting in large power consumption.
A primary object of the present invention is, therefore, to provide a semiconductor memory device having a small occupied area and power consumption.
A semiconductor memory device according to the present invention includes first and second inverters having output nodes connected to first and second storage nodes respectively; a first switching circuit rendering conductive between the first storage node and an input node of the second inverter and applying a second potential to an input node of the first inverter if first and second potentials are applied to the first and second storage nodes respectively, rendering conductive between the second storage node and the input node of the first inverter and applying the second potential to the input node of the second inverter if the second and first potentials are applied to the first and second storage nodes respectively, and applying the second potential to each of the input nodes of the first and second inverters if the first potential is applied to each of the first and second storage nodes; and a second switching circuit rendering conductive between the first bit line and the first storage node and between the second bit line and the second storage node, in response to the word line being set to a selective level. Thus, the semiconductor memory device has three types of storing/holding states, i.e., a state where the first and second potentials are stored into the first and second storage nodes respectively, a state where the, second and first potentials are stored into the first and second storage nodes respectively, and a state where the first potential is stored into each of the first and second storage nodes. Accordingly, compared to the conventional case where two semiconductor memory devices (memory cells) including two inverters were required to hold three kinds of data signals, the number of transistors can be reduced. This allows reduction of the occupied area. Moreover, the number of bit lines can also be reduced, so that reduction in an amount of charging/discharging of bit lines may also be expected, leading to lower power consumption.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.